As an external storage device used in a computer system, an SSD (Solid State Drive) mounted with a nonvolatile semiconductor memory such as a NAND-type flash memory attracts attention. The flash memory has advantages such as high speed and light weight compared with a magnetic disk device.
The SSD includes a plurality of flash memory chips, a controller that performs read/write control for the respective flash memory chips in response to a request from a host apparatus, a buffer memory for performing data transfer between the respective flash memory chips and the host apparatus, a power supply circuit, and a connection interface to the host apparatus (e.g., Japanese Patent 3688835).
Like the NAND flash memory, there is a nonvolatile semiconductor memory device that, in storing data, erases data in a unit called a block and then performs writing, a nonvolatile semiconductor memory device that performs readout and writing in a unit called a page, and a nonvolatile semiconductor memory device in which a unit of erasing, readout, and writing is fixed.
On the other hand, a unit for a host apparatus such as a personal computer to read out data from and write data in a secondary storage device such as a hard disk is called a sector. The sector is set independently from a unit of erasing, readout, and writing of a semiconductor memory device.
For example, whereas a size of a block (a block size) of the semiconductor memory device is 512 kilobytes (KB) and a size of a page (a page size) thereof is 4 KB, a size of a sector (a sector size) of the host apparatus is set to 512 bytes (B).
In this way, the unit of erasing, readout, and writing of the semiconductor memory device may be larger than the unit of readout and writing of the host apparatus.
When the secondary storage device of the personal computer such as the hard disk is configured by using such a semiconductor memory device, it is necessary to adapt small-sized data from the personal computer as the host apparatus to the block size and the page size of the semiconductor memory device and subject the data to address translation.
A flash memory has a tendency that deterioration of cells proceeds according to an increase in the number of times of erasing of a block performed prior to data writing. Therefore, processing called wear leveling is performed for equally dispersing data update sections in a semiconductor memory device such that the numbers of times of erasing of all the cells in the semiconductor memory device are generally equalized.
When a large-capacity secondary storage device is configured by using such a flash memory, in performing the address translation, if a unit of the data management is a small size (e.g., the page size), the size of management tables increases and does not fit in a main memory of a controller of the secondary storage device. Address translation cannot be performed at high speed. In this way, the size of the management tables inevitably increases according to an increase in capacity of the NAND flash memory as the secondary storage device. Therefore, there is a demand for a method of reducing a capacity of the management tables as much as possible and increasing speed of search processing by the management tables.
In the SSD, as disclosed in U.S. Patent Application Publication Number 2005/0195635, a cache memory is often interposed between the flash memory and the host apparatus to reduce the number of times of writing (the number of times of erasing) in the flash memory. When writing in the cache memory from the host apparatus is performed, if the cache memory is full, data is written in the cache memory after data is flushed from the cache memory to the flash memory. In this way, in the case of the cache memory for writing, unlike the cache memory for readout, flush processing for flushing data to the flash memory is performed. Therefore, processing is complicated, the size of management tables thereof increases, and search processing for the management tables takes long.